1. Field of the Invention
The present invention relates to a drive circuit of a display apparatus which has a frame memory.
2. Description of the Related Art
FIG. 1 shows an example of a data line drive circuit of a display apparatus such as a liquid crystal display of a portable phone, in which a plurality of scanning lines and a plurality of data lines are arranged like a lattice. A shift register circuit 901 generates a sampling signal in synchronism with a signal DCLK when a horizontal start signal STH is supplied. Image data D0-17 are latched in a data latch circuit A 902 in synchronism with the sampling signal in order and the latched image data are latched in a data latch circuit B 903 at a time in response to the horizontal signal STB. The image data latched in the data latch circuit B903 are decoded by a decoder circuit 904. A gradation voltage selection circuit 905 is connected to the decoder circuit 904 and selects gradation switches in accordance with the decoded image data. A gradation voltage generating circuit 908 has a plurality of resistors connected in series and generates a plurality of voltages suitable for use as the gradation voltages in the display apparatus. A buffer amplifier 909 converts the voltages generated by the gradation voltage generating circuit 908 by using a voltage follower circuit, and drives the data lines of the display apparatus through the gradation voltage selection circuit 905.
Because the voltage used to drive the display apparatus such as the liquid crystal display is generally higher than the voltage to be used in a logic circuit section such as the shift register circuit and the data latch circuit, the drive circuit needs to incorporate therein a level shift circuit. In this case, the level shift circuit is provided before or after the decoder circuit from the viewpoint of reduction in the number of bits of the image data and power consumption. For example, when the image data is of 6 bits (26=64 gradations) and the level shift circuit is disposed downstream (when viewing circuit components in a data stream direction) relative to the decoder circuit, [data latch circuit B], [decoder circuit (64×6-input NAND)], and [64 level shift circuits] are arranged in this order, causing the drive circuit to have 64 level shift circuits. On the other hand, if the level shift circuit is arranged upstream relative to the decoder circuit, and [data latch circuit B], [level shift circuit (6)], and [decoder circuit] are arranged in this order, causing the drive circuit to have only 6 level shift circuits. Because large transient current flows through the level shift circuit, a display apparatus incorporated in such a way in a mobile phone is preferably designed to include as small number of level shift circuits as possible in terms of reduction in power consumption. Accordingly, when the image data is of 4 bits or more, the level shift circuit is generally disposed upstream relative to the decoder circuit.
However, when the level shift circuit is disposed upstream relative to the decoder circuit in this way, circuits to be disposed downstream relative to the level shift circuit need to be fabricated with high-voltage endurance. Therefore, a new problem arises in that the scale of drive circuit becomes large. In order to solve this problem, as shown in FIG. 2, it could be considered that bits of the image data are divided into three upper bits and three lower bits to make the circuit scale of the decoder circuit small. That is, 64 gradation switches 922 are controlled based on the three upper bits and are connected to the gradation voltages of V1 to V64 respectively. Eight gradations are selected from among the 64 gradations based on the three lower bits and one gradation is further selected from among the eight gradations based on the 3 upper bits. The decoder circuit is composed of (64+8) number of 3-input NAND circuits 920.
An example of a method of reducing the power consumption of the drive circuit would be a technique disclosed in Japanese Laid Open Patent Application (JP-P2002-108301A). In this conventional example, image data D0-D17 are determined and the power consumption of buffer amplifiers (voltage follower circuits) which are not used is reduced by an amplifier enable circuit. The image data are supplied in synchronism with a clock signal DCLK. FIG. 3 shows the detail when the technique for reducing the power consumption is applied to a gradation data determination circuit 906 shown in FIG. 1. The gradation data determination circuit 906 is composed of a decoder circuit 910 which is composed of three 6-input NAND circuits and one 3-input NAND circuit, and an RS latch circuit 911 which is connected to the decoder circuit. The reason why the three 6-input NAND circuits are used is that the image data is transferred in units of pixels and the image data has a 6-bit width to represent red, green, and blue for color display. When data is transferred in units of two pixels, the seven (=6+1) sets of 6-input NAND circuits are necessary. Because liquid crystal display device is not a device capable of emitting light and in addition, a drive voltage is the same irrespective of color to be displayed, 64 decoder circuits 910 and 64 RS latch circuits 911 are necessary. Signs of “00H” and “3FH” included in the decoder circuit and shown in FIG. 24 means that image data is represented by “000000=00H” and “111111=3FH” (hereinafter, in case of hexadecimal notation, H is added).
The gradation data determination circuit 906 is configured so that image data buses D0-D17 are connected to the decoder circuit 910 and the determination circuit 906 carries out determination in synchronism with a clock signal DCLK. For example, when even only one “00H” is inputted as image data to the circuit 906 during one horizontal period, the data “00H” is set in the RS latch circuit and the buffer amplifier corresponding to “00H” is set to an enable state by the amplifier enable circuit. If no “00H” is inputted thereto during the one horizontal period, the buffer amplifier corresponding to “00H” is set to a disable state, allowing reduction in the magnitude of current consumed in the buffer amplifier. This determination is carried out every horizontal period and a reset signal is supplied every horizontal period to initialize the data contained in the RS latch circuit. In this way, determining the value of image data in synchronism with the clock signal DCLK to set the buffer amplifier corresponding to a gradation, which is not used during the corresponding horizontal period, to the disable state helps to reduce the consumption current.
In such a technique, the image data is always latched in a line memory (the data latch circuit A and the data latch circuit B) in synchronism with a signal from the CPU. Also, the determination of the image data is carried out in synchronism with the signal from the CPU. However, a portable phone displays a still image in most of the cases and therefore is configured so that a data drive circuit section includes a frame memory and CPU sends image data only when frame image is changed, in order to reduce power consumption. For this reason, a control signal for control of drive circuit and a signal from the CPU are made asynchronous. In other words, a clock signal and image data are supplied only when an image to be displayed is changed. However, in order to display an image, the image data must be driven in a constant period asynchronous with a signal from the CPU. The image data are transferred from the frame memory to the line memory all at once in response to a latch signal having the constant period. Therefore, it is necessary to determine the image data stored in the line memory all at once. However, the conventional technique cannot provide a method for determining image data stored in the line memory all at once.
In conjunction with the above description, a drive circuit of a liquid crystal display is disclosed in Japanese Laid Open Patent Application (JP-P2001-272655A). In this conventional example, one is selected from gradation voltages for 2n gradations to a positive polarity and a negative polarity to a common voltage as a drive voltage of data lines of a liquid crystal panel based on n-bit digital data signal by using an A/D converter. A drive capability is increased by an operational amplifier of a voltage follower connection which can output a rising waveform and a falling waveform, and the gradation voltage is outputted from an output terminal. When the polarity of this output changes every a predetermined period, the output terminal is connected to the common voltage. The input of the operational amplifier is set as the gradation voltage for the next polarity in which the current flowing through the operational amplifier becomes the smallest during a period from when the output terminal is connected to the common voltage to when the next gradation voltage for the next polarity is selected by the D/A converter.
Also, a drive apparatus of a liquid crystal display is disclosed in Japanese Laid Open Patent Application (JP-P2001-343944A). In this conventional example, k-bit data signal corresponding to data lines of a liquid crystal panel is converted to a desired one of 2k gradation voltages by a D/A converter which is alternately switched between a positive polarity and a negative polarity for every scan of the data lines. The drive capability of the gradation voltage is increased by a voltage follower output circuit, and the gradation voltage is outputted to the data lines. A logical process is applied to the data signal for n-th scanning and the data signal for (n+1)-th scanning, and the through rate of the voltage follower output circuit in the (n+1)-th scanning is changed in accordance with the logical process result.
Also, a drive circuit of a liquid crystal display is disclosed in Japanese Laid Open Patent Application (JP-P2002-215108A). In this conventional example, a digital video image data is outputted as it is or is outputted after inversion based on a polarity signal which is inverted for every horizontal synchronization period or vertical synchronization period. A group of gradation voltages for the positive polarity and a group of gradation voltages for the negative polarity are predetermined to fit with the transmittivity characteristic to the positive application voltage and the transmittivity characteristic to the negative application voltage in the liquid crystal display, and one is selected from the above groups based on the polarity signal. One is selected from among the gradation voltages of the selected group based on the digital video image data or the inverted digital video image data, and the selected gradation voltage is applied to a corresponding data electrode.
Also, a drive circuit is disclosed in Japanese Laid Open Patent Application (JP-P2002-366106A). In this conventional example, a scanning line inversion drive is carried out to set a voltage level in a scanning period of a counter electrode opposing to a pixel electrode through electro-optical substance to a voltage level different from that in a previous scanning period. In the M-th scanning period, the voltage level of the counter electrode is set to one of first and second voltage levels. In a virtual scanning period next to the M-th scanning period, the voltage level of the counter electrode is set to the other of the first and second voltage levels. In the first scan period after the virtual scanning period, the voltage level of the counter electrode is set to the one voltage level of the first and second voltage levels.